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RL78/G1A CHAPTER 21 VOLTAGE DETECTOR
21.4.3 When used as interrupt & reset mode
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Specify the operation mode (the interrupt & reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage (VLVDH, VLVDL)
by using the option byte 000C1H.
The operation is started in the following initial setting state when the interrupt & reset mode is set.
• Bit 7 (LVISEN) of the voltage detection register (LVIM) is set to 0 (disable rewriting of voltage detection level
register (LVIS))
• The initial value of the voltage detection level select register (LVIS) is set to 00H.
Bit 7 (LVIMD) is 0 (interrupt mode).
Bit 0 (LVILV) is 0 (high-voltage detection level: V
LVDH).
• Operation in LVD interrupt & reset mode
In the interrupt & reset mode (option byte LVIMDS1, LVIMDS0 = 1, 0), the state of an internal reset by LVD is
retained until the supply voltage (V
DD) exceeds the high-voltage detection level (VLVDH) after power is supplied.
The internal reset is released when the supply voltage (V
DD) exceeds the high-voltage detection level (VLVDH).
At the fall of the operating voltage, an interrupt request signal (INTLVD) by LVD is generated and arbitrary save
processing is performed when the supply voltage (V
DD) falls below the high-voltage detection level (VLVDH). After
that, an internal reset by LVD is generated when the supply voltage (V
DD) falls below the low-voltage detection
level (V
LVDL). However, after INTLVD is generated, an interrupt request signal is not generated even if the supply
voltage becomes equal to or higher than the high-voltage detection voltage (VLVDH) without falling below the low-
voltage detection voltage (V
LVDL).
To use the LVD reset & interrupt mode, perform the processing according to Figure 21-7 Processing
Procedure After an Interrupt Is Generated and Figure 21-8 Initial Setting of Interrupt and Reset Mode.
Figure 21-6 shows the timing of the internal reset signal and interrupt signal generated in the LVD interrupt & reset
mode.
R01UH0305EJ0200 Rev.2.00 764
Jul 04, 2013