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RL78/G1A CHAPTER 22 SAFETY FUNCTIONS
Figure 22-1. Format of Flash Memory CRC Control Register (CRC0CTL)
Address: F02F0H After reset: 00H R/W
Symbol <7> 6 5 4 3 2 1 0
CRC0CTL CRC0EN 0 FEA5 FEA4 FEA3 FEA2 FEA1 FEA0
CRC0EN Control of CRC ALU operation
0 Stop the operation.
1 Start the operation according to HALT instruction execution.
FEA5 FEA4 FEA3 FEA2 FEA1 FEA0 High-speed CRC operation range
0 0 0 0 0 0 00000H to 03FFBH (16 Kbytes - 4 bytes)
0 0 0 0 0 1 00000H to 07FFBH (32 Kbytes - 4 bytes)
0 0 0 0 1 0 00000H to 0BFFBH (48 Kbytes - 4 bytes)
0 0 0 0 1 1 00000H to 0FFFBH (64 Kbytes - 4 bytes)
Other than above Setting prohibited
Remark Input the expected CRC operation result value to be used for comparison in the lowest 4 bytes of the flash
memory. Note that the operation range will thereby be reduced by 4 bytes.
22.3.1.2 Flash memory CRC operation result register (PGCRCL)
This register is used to store the high-speed CRC operation results.
The PGCRCL register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 22-2. Format of Flash Memory CRC Operation Result Register (PGCRCL)
Address: F02F2H After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8
PGCRCL PGCRC15 PGCRC14 PGCRC13 PGCRC12 PGCRC11 PGCRC10 PGCRC9 PGCRC8
7 6 5 4 3 2 1 0
PGCRC7 PGCRC6 PGCRC5 PGCRC4 PGCRC3 PGCRC2 PGCRC1 PGCRC0
PGCRC15 to 0 High-speed CRC operation results
0000H to FFFFH Store the high-speed CRC operation results.
Caution The PGCRCL register can only be written if CRC0EN (bit 7 of the CRC0CTL register) = 1.
Figure 22-3 shows the flowchart of flash memory CRC operation function (high-speed CRC).
R01UH0305EJ0200 Rev.2.00 774
Jul 04, 2013