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RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 417
Jul 04, 2013
Figure 12-8. Format of Serial Data Register mn (SDRmn)
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Address: FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03), After reset: 0000H R/W
FFF48H, FFF49H (SDR10)
Note
, FFF4AH, FFF4BH (SDR11)
Note
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0
SDRmn[15:9] Transfer clock setting by dividing the operating clock (fMCK)
0 0 0 0 0 0 0 fMCK/2
0 0 0 0 0 0 1 fMCK/4
0 0 0 0 0 1 0 fMCK/6
0 0 0 0 0 1 1 fMCK/8
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1 1 1 1 1 1 0 fMCK/254
1 1 1 1 1 1 1 fMCK/256
Note 32, 48, and 64-pin products
Cautions 1. Be sure to clear bit 8 of the SDR02, SDR03, SDR10, and SDR11 to “0”.
2. Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used.
3. Setting SDRmn[15:9] = 0000000B is prohibited when simplified I
2
C is used. Set SDRmn[15:9]
to 0000001B or greater.
4. Do not write eight bits to the lower eight bits if operation is stopped (SEmn = 0). (If these bits
are written to, the higher seven bits are cleared to 0.)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
FFF11H (SDR00)
FFF45H (SDR02)
FFF44H (SDR02)
<R>
<R>
<R>