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RL78/G1A CHAPTER 3 CPU ARCHITECTURE
R01UH0305EJ0200 Rev.2.00 71
Jul 04, 2013
Table 3-5. SFR List (5/5)
Manipulable Bit Range Address
Special Function Register (SFR) Name
Symbol R/W
1-bit 8-bit 16-bit
After Reset
FFFD0H IF2L R/W
√ √
00H
FFFD1H
Interrupt request flag register 2
IF2H
IF2
R/W
√ √
√
00H
FFFD4H MK2L R/W
√ √
FFH
FFFD5H
Interrupt mask flag register 2
MK2H
MK2
R/W
√ √
√
FFH
FFFD8H PR02L R/W
√ √
FFH
FFFD9H
Priority specification flag
register 02
PR02H
PR02
R/W
√ √
√
FFH
FFFDCH PR12L R/W
√ √
FFH
FFFDDH
Priority specification flag
register 12
PR12H
PR12
R/W
√ √
√
FFH
FFFE0H IF0L R/W
√ √
00H
FFFE1H
Interrupt request flag register 0
IF0H
IF0
R/W
√ √
√
00H
FFFE2H IF1L R/W
√ √
00H
FFFE3H
Interrupt request flag register 1
IF1H
IF1
R/W
√ √
√
00H
FFFE4H MK0L R/W
√ √
FFH
FFFE5H
Interrupt mask flag register 0
MK0H
MK0
R/W
√ √
√
FFH
FFFE6H MK1L R/W
√ √
FFH
FFFE7H
Interrupt mask flag register 1
MK1H
MK1
R/W
√ √
√
FFH
FFFE8H PR00L R/W
√ √
FFH
FFFE9H
Priority specification flag
register 00
PR00H
PR00
R/W
√ √
√
FFH
FFFEAH PR01L R/W
√ √
FFH
FFFEBH
Priority specification flag
register 01
PR01H
PR01
R/W
√ √
√
FFH
FFFECH PR10L R/W
√ √
FFH
FFFEDH
Priority specification flag
register 10
PR10H
PR10
R/W
√ √
√
FFH
FFFEEH PR11L R/W
√ √
FFH
FFFEFH
Priority specification flag
register 11
PR11H
PR11
R/W
√ √
√
FFH
FFFF0H
FFFF1H
Multiplication/division data
register A (L)
MDAL R/W
− − √
0000H
FFFF2H
FFFF3H
Multiplication/division data
register A (H)
MDAH R/W
− − √
0000H
FFFF4H
FFFF5H
Multiplication/division data
register B (H)
MDBH R/W
− − √
0000H
FFFF6H
FFFF7H
Multiplication/division data
register B (L)
MDBL R/W
− − √
0000H
FFFFEH Processor mode control
register
PMC R/W
√ √ −
00H
Remark For extended SFRs (2nd SFRs), see Table 3-6 Extended SFR (2nd SFR) List.