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RL78/G1A CHAPTER 3 CPU ARCHITECTURE
R01UH0305EJ0200 Rev.2.00 94
Jul 04, 2013
Figure 3-38. Example of RET
RET
(SP+3)
SP
F0000H
(SP+2)
SP+3
SP+2
PC
SP
(SP+1)
(SP)
SP+1
SP
SP+4
Stack
area
Memory
OP-code
<1>
<1>
Instruction code
<2>
<3>
Stack addressing is specified <1>.
The contents of addresses SP, SP + 1, and SP + 2 are stored
in PC bits 7 to 0, 15 to 8, and 19 to 16, respectively <2>.
The value of SP <3> is increased by four.
Figure 3-39. Example of Interrupt, BRK
PSW
SP
F0000H
PC19㧙PC16
PC
SP
PC15㧙PC8
PC7㧙PC0
or
PSW
SP㧙1
SP㧙2
SP㧙3
SP㧙4
OP-code
<1>
<2>
<2>
Stack
area
Memory
Instruction code
Interrupt
<3>
Stack addressing is specified <1>. In response to a BRK
instruction or acceptance of an interrupt, the value of the
program counter (PC) changes to indicate the address of
the next instruction.
The values of the PSW, PC bits 19 to 16, 15 to 8, and 7 to
0 are stored in addresses SP – 1, SP – 2, SP – 3, and
SP – 4, respectively <2>.
The value of the SP <3> is decreased by 4.