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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 229
Jul 04, 2013
(5) Operation of capture & one-count mode (high-level width measurement)
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit of timer channel start register m (TSm).
<2> Timer count register mn (TCRmn) holds the initial value until start trigger generation.
<3> Rising edge of the TImn input is detected.
<4> On start trigger detection, the value of 0000H is loaded to the TCRmn register and count starts.
<5> On detection of the falling edge of the TImn input, the value of the TCRmn register is captured to timer data
register mn (TDRmn) and INTTMmn is generated.
Figure 6-29. Operation Timing (In Capture & One-count Mode : High-level Width Measurement)
Remarks 1. The timing is shown in Figure 6-27 indicates while the noise filter is not used. By making the noise
filter on-state, the edge detection becomes 2 f
MCK cycles (it sums up to 3 to 4 cycles) later than the
normal cycle of TImn input. The error per one period occurs by the asynchronous between the
period of the TImn input and that of the count clock (f
MCK).
2. m: Unit number (m = 0), n: Channel number (n = 0 to 7 (however, timer input pin (TImn), timer output
pin (TOmn) : n = 0, 1, 3 to 7))
fMCK
(fTCLK)
TSmn (write)
TEmn
TImn input
<1>
<2>
Rising edge
Edge detection
<4>
TCRmn
Initial value
m−1
m
TDRmn
Start trigger
detection signal
<3>
Falling edge
0000
m
Edge detection
0000
m+1
INTTMmn
<5>