Filter
Top Products
RL78/G1A CHAPTER 5 CLOCK GENERATOR
R01UH0305EJ0200 Rev.2.00 153
Jul 04, 2013
Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/3)
Address: F00F0H After reset: 00H R/W
Symbol <7> 6 <5> <4> <3> <2> 1 <0>
PER0 RTCEN 0 ADCEN IICA0EN SAU1EN SAU0EN 0 TAU0EN
ADCEN Control of A/D converter input clock supply
0
Stops input clock supply.
• SFR used by the A/D converter cannot be written.
• The A/D converter is in the reset status.
1
Enables input clock supply.
• SFR used by the A/D converter can be read and written.
IICA0EN Control of serial interface IICA0 input clock supply
0
Stops input clock supply.
• SFR used by the serial interface IICA0 cannot be written.
• The serial interface IICA0 is in the reset status.
1
Enables input clock supply.
• SFR used by the serial interface IICA0 can be read and written.
SAU1EN Control of serial array unit 1 input clock supply
0
Stops input clock supply.
• SFR used by the serial array unit 1 cannot be written.
• The serial array unit 1 is in the reset status.
1
Enables input clock supply.
• SFR used by the serial array unit 1 can be read and written.
Caution Be sure to clear the following bits to 0.
25-pin products: bits 1, 3, 6
32, 48, 64-pin products: bits 1, 6