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RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 556
Jul 04, 2013
(2) Processing flow
Figure 12-108. Timing Chart of Data Transmission
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6
SSmn
SEmn
SOEmn
SDRmn
SCLr output
SDAr output
SDAr input
Shift
register mn
INTIICr
TSFmn
D5 D4 D3 D2 D1 D0
ACK
Shift operation
“L”
“H”
“H”
Transmit data 1
Figure 12-109. Flowchart of Simplified I
2
C Data Transmission
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21),
mn = 00 to 03, 10, 11
Starting data transmission
Data transmission
completed
Transfer end interrupt
g
enerated?
No
Yes
Writing data to SIOr
(SDRmn[7:0])
No
Yes
Stop condition generation
Data transfer completed?
Yes
No
Address field
transmission completed
Responded ACK?
Communication error
processing
Wait for transmission complete.
(Clear the interrupt request flag)
Transmission start by writing.
ACK acknowledgment from the slave
If ACK (PEF = 0), to the next process
if NACK (PEF = 1), to error handling