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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 191
Jul 04, 2013
Figure 6-2. Internal Block Diagram of Channel 0, 2, 4, 6 of Timer Array Unit 0
PMxx
CKS0n0
CCS0n
MAS
TER0n
STS0n2
STS0n1
STS0n0
MD0n2CIS0n1CIS0n0
MD0n3
MD0n1MD0n0
OVF
0n
CK00
CK01
f
MCK
f
TCLK
Interrupt
controller
Output
controller
Output latch
(Pxx)
INTTM0n
(Timer interrupt)
TO0n
Timer status
register 0n (TSR0n)
Overflow
Timer data register 0n (TDR0n)
Timer counter register 0n (TCR0n)
Timer mode register 0n (TMR0n)
Channel n
Timer controller
Trigger
selection
Count clock
selection
Mode
selection
Slave/master
controller
Edge
detection
Operating
clock selection
TI0n
Interrupt signal from master channel
Note1
Interrupt signal to slave channel
Note2
CKS0n1
Notes 1. Channels 2, 4, 6 only
2. n = 2, 4, 6 only
Remark n = 0, 2, 4, 6
Figure 6-3. Internal Block Diagram of Channels 1 and 3 of Timer Array Unit 0
TO0n
PMxx
STS0n2STS0n1 STS0n0 MD0n2CIS0n1CIS0n0 MD0n3 MD0n1 MD0n0
OVF
0n
INTTM0n
(Timer interrupt)
CK00
CK01
f
MCK
f
TCLK
CK02
CK03
INTTM0nH
(Timer interrupt)
Interrupt
controller
Output
controller
Output latch
(Pxx)
Timer status
register 0n (TSR0n)
Overflow
Timer data register 0n (TDR0n)
Timer counter register 0n (TCR0n)
Timer mode register 0n (TMR0n)
Channel n
Timer controller
Trigger
selection
Count clock
selection
Mode
selection
Edge
detection
Operating
clock selection
Interrupt signal from the master channel
8-bit timer
controller
Mode
selection
Interrupt
controller
TI0n
CKS0nCKS1n CCS0n
SPLIT
0n
Remark n = 1, 3
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