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RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (T
A = −40 to +85°C)
R01UH0305EJ0200 Rev.2.00 887
Jul 04, 2013
(9) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
HS
Note 1
LS
Note 2
LV
Note 3
Parameter Symbol Conditions
MIN. MAX. MIN. MAX. MIN. MAX.
Unit
24 MHz < fMCK
20/f
MCK
−
−
ns
20 MHz < f
MCK
≤
24 MHz
16/fMCK
−
−
ns
16 MHz < f
MCK
≤
20 MHz
14/fMCK
−
−
ns
8 MHz < f
MCK
≤
16 MHz
12/fMCK
−
−
ns
4 MHz < f
MCK
≤
8 MHz
8/fMCK 16/fMCK
−
ns
2.7 V
≤
EV
DD0
≤
3.6 V,
2.3 V
≤
V
b
≤
2.7 V
fMCK ≤ 4 MHz
6/fMCK 10/fMCK 10/fMCK ns
24 MHz < fMCK
48/f
MCK
−
−
ns
20 MHz < f
MCK
≤
24 MHz
36/fMCK
−
−
ns
16 MHz < f
MCK
≤
20 MHz
32/fMCK
−
−
ns
8 MHz < f
MCK
≤
16 MHz
26/fMCK
−
−
ns
4 MHz < f
MCK
≤
8 MHz
16/fMCK 16/fMCK
−
ns
SCKp cycle time
Note 4
tKCY2
1.8 V
≤
EV
DD0
< 3.3 V,
1.6 V
≤
V
b
≤
2.0 V
Note 5
f
MCK
≤
4 MHz
10/fMCK 10/fMCK 10/fMCK ns
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V
t
KCY2/2
− 18
t
KCY2/2
− 50
t
KCY2/2
− 50
ns SCKp high-/low-level
width
tKH2,
t
KL2
1.8 V ≤ EV
DD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Note 5
t
KCY2/2
− 50
t
KCY2/2
− 50
t
KCY2/2
− 50
ns
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V
1/f
MCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
ns SIp setup time
(to SCKp↑)
Note 6
t
SIK2
1.8 V ≤ EV
DD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Note 5
1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK
+ 30
ns
SIp hold time
(from SCKp↑)
Note 6
t
KSI2 1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK
+ 31
ns
2.7 V ≤ EVDD0
≤
3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
2/f
MCK
+ 214
2/fMCK
+ 573
2/fMCK
+ 573
ns Delay time from SCKp↓
to SOp output
Note 7
t
KSO2
1.8 V ≤ EV
DD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Note 5
,
C
b = 30 pF, Rb = 5.5 kΩ
2/f
MCK
+ 573
2/fMCK
+ 573
2/fMCK
+ 573
ns
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
5. Use it with EV
DD0 ≥ Vb.
6. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time or SIp hold time
becomes “from SCKp↓“ when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
7. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑“ when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (V
DD tolerance
(When 25- to 48-pin products)/EV
DD tolerance (When 64-pin products)) mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg). For V
IH and VIL, see the DC
characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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