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RL78/G1A CHAPTER 7 REAL-TIME CLOCK
7.3.1 Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware
macro that is not used is stopped in order to reduce the power consumption and noise.
When the real-time clock is used, be sure to set bit 7 (RTCEN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> 6 <5> <4> <3> <2> 1 <0>
PER0 RTCEN 0 ADCEN IICA0EN
SAU1EN
Note
SAU0EN 0 TAU0EN
RTCEN Control of real-time clock (RTC) and 12-bit interval timer input clock supply
0
Stops input clock supply.
• SFR used by the real-time clock (RTC) and 12-bit interval timer cannot be written.
• The real-time clock (RTC) and 12-bit interval timer are in the reset status.
1
Enables input clock supply.
• SFR used by the real-time clock (RTC) and 12-bit interval timer can be read and written.
Note 32, 48, and 64-pin products only.
Cautions 1. When using the real-time clock, first set the RTCEN bit to 1 and then set the following
registers, while oscillation of the count clock (f
RTC) is stable. If RTCEN = 0, writing to
the control registers of the real-time clock is ignored, and, even if the registers are
read, only the default values are read (except for the subsystem clock supply mode
control register (OSMC), port mode register 3 (PM3), port register 3 (P3)).
<R>
• Real-time clock control register 0 (RTCC0)
• Real-time clock control register 1 (RTCC1)
• Second count register (SEC)
• Minute count register (MIN)
• Hour count register (HOUR)
• Day count register (DAY)
• Week count register (WEEK)
• Month count register (MONTH)
• Year count register (YEAR)
• Watch error correction register (SUBCUD)
• Alarm minute register (ALARMWM)
• Alarm hour register (ALARMWH)
• Alarm week register (ALARMWW)
2. The subsystem clock supply to peripheral functions other than the real-time clock
and 12-bit interval timer can be stopped in STOP mode or HALT mode when the
subsystem clock is used, by setting the RTCLPC bit of the subsystem clock supply
mode control register (OSMC) to 1.
<R>
3. Be sure to clear the following bits to 0.
25-pin products: bits 1, 3, 6
32, 48, 64-pin products: bits 1, 6
R01UH0305EJ0200 Rev.2.00 296
Jul 04, 2013