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RL78/G1A CHAPTER 28 INSTRUCTION SET
R01UH0305EJ0200 Rev.2.00 838
Jul 04, 2013
Table 28-5. Operation List (6/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (f
CLK) when the code flash memory is accessed, or when the data flash memory is
accessed by an 8-bit instruction.
3. Except rp = AX
4. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
BC, !addr16 3 1 4 BC ← (addr16)
BC, ES:!addr16 4 2 5 BC ← (ES, addr16)
DE, !addr16 3 1 4 DE ← (addr16)
DE, ES:!addr16 4 2 5 DE ← (ES, addr16)
HL, !addr16 3 1 4 HL ← (addr16)
HL, ES:!addr16 4 2 5 HL ← (ES, addr16)
BC, saddrp 2 1
−
BC ← (saddrp)
DE, saddrp 2 1
−
DE ← (saddrp)
MOVW
HL, saddrp 2 1
−
HL ← (saddrp)
XCHW AX, rp
Note 3
1 1
−
AX ←→ rp
AX 1 1
−
AX ← 0001H ONEW
BC 1 1
−
BC ← 0001H
AX 1 1
−
AX ← 0000H
16-bit
data
transfer
CLRW
BC 1 1
−
BC ← 0000H
A, #byte 2 1
−
A, CY ← A + byte × × ×
saddr, #byte 3 2
−
(saddr), CY ← (saddr)+byte × × ×
A, r
Note 4
2 1
−
A, CY ← A + r × × ×
r, A 2 1
−
r, CY ← r + A × × ×
A, !addr16 3 1 4 A, CY ← A + (addr16) × × ×
A, ES:!addr16 4 2 5 A, CY ← A + (ES, addr16) × × ×
A, saddr 2 1
−
A, CY ← A + (saddr) × × ×
A, [HL] 1 1 4 A, CY ← A+ (HL) × × ×
A, ES:[HL] 2 2 5 A,CY ← A + (ES, HL) × × ×
A, [HL+byte] 2 1 4 A, CY ← A + (HL+byte) × × ×
A, ES:[HL+byte] 3 2 5 A,CY ← A + ((ES, HL)+byte) × × ×
A, [HL+B] 2 1 4 A, CY ← A + (HL+B) × × ×
A, ES:[HL+B] 3 2 5 A,CY ← A+((ES, HL)+B) × × ×
A, [HL+C] 2 1 4 A, CY ← A + (HL+C) × × ×
8-bit
operation
ADD
A, ES:[HL+C] 3 2 5 A,CY ← A + ((ES, HL) + C) × × ×
<R>