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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 278
Jul 04, 2013
Figure 6-71. Example of Basic Timing of Operation as PWM Function
TSmn
TEmn
TDRmn
TCRmn
TOmn
INTTMmn
a b
0000H
TSmp
TEmp
TDRmp
TCRmp
TOmp
INTTMmp
c
c
d
0000H
c
d
Master
channel
Slave
channel
a+1
a+1
b+1
FFFFH
FFFFH
Remark 1. m: Unit number (m = 0), n: Channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p ≤ 7)
However, timer output pin (TOmp) : p = 1, 3 to 7
2. TSmn, TSmp: Bit n, p of timer channel start register m (TSm)
TEmn, TEmp: Bit n, p of timer channel enable status register m (TEm)
TCRmn, TCRmp: Timer count registers mn, mp (TCRmn, TCRmp)
TDRmn, TDRmp: Timer data registers mn, mp (TDRmn, TDRmp)
TOmn, TOmp: TOmn and TOmp pins output signal