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CHAPTER 4 NDA-24282
Page 76
Revision 1.0
PA-CP54 (CPU)
SW2
1
2
3
ON × When equipping 1M bit SRAM IC.
OFF When equipping 256 K bit SRAM IC.
4
5
6
ON ×
When providing EE0000H ~ EFFFFFH and
E00000H ~ E3FFFFH as RAM areas.
OFF
When providing EE0000H ~ EFFFFFH as
RAM area.
7
ON ×
When equipping 256 kbit SRAM IC as parity
RAM.
OFF
When equipping 64 kbit SRAM IC as parity
RAM.
8
ON Test mode (Always mis-hit state).
OFF × Normal operation mode.
SW3
1OFF× Fixed.
2
ON
When equipping 64 kbit SRAM IC as parity
RAM.
OFF ×
When equipping 256 kbit SRAM IC as parity
RAM.
3
ON ×
When equipping EPROM IC of either 1M bit
2M bit.
OFF When equipping EPROM IC of 4M bit.
4
ON ×
When equipping EPROM IC of either 1M bit
2M bit as parity ROM.
OFF
When equipping EPROM IC of 4M bit as pari-
ty ROM.
SWITCH
NAME
SWITCH NO. SETTING
STANDARD
SETTING
MEANING
SW2-1 SW2-2 SETTING OF EPROM
ON ON When equipping 1M bit EPROM IC.
ON OFF When equipping 2M bit EPROM IC (standard).
OFF ON When equipping 4M bit EPROM IC.
OFF OFF Not used
SW2-4 SW2-5 SETTING OF ROM AREAS
ON ON When providing 1MB of F00000H ~ FFFFFFH.
OFF ON
When providing 2MB of F00000H ~ FFFFFFH and 00000H ~
0FFFFFH (standard setting).
OFF OFF
When providing 4MB of F00000H ~ FFFFFFH and 00000H ~
2FFFFFH.