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NDA-24282 CHAPTER 4
Page 75
Revision 1.0
PA-CP54 (CPU)
SW0
1
ON × Memory Parity Alarm Inhibited.
OFF Memory Parity Alarm not inhibited.
2
ON External NMI input inhibited.
OFF × External NMI input not inhibited.
3
ON Memory Alarm NMI inhibited.
OFF × Memory Alarm NMI not inhibited.
4
ON COPALM inhibited.
OFF × COPALM not inhibited.
5OFF× Fixed.
6OFF× Fixed.
7
ON
When ACDP is provided by dual-system con-
figuration.
OFF
When ACDP is provided by single-system con-
figuration.
8OFF× Fixed.
SW1
1
ON
Sets Ready Alarm Detect Timing to longer than
48 sec.
OFF ×
Sets Ready Alarm Detect Timing to longer than
6 sec.
2
ON Sets the interval of C-Level interrupt to 4 msec.
OFF ×
Sets the interval of C-Level interrupt to 16
msec.
3
ON
NMI input from an external memory system is
inhibited.
OFF ×
NMI input from an external memory system is
not inhibited.
4OFF× Fixed.
5
ON × Equipped with 1.5 MB CRAM area.
OFF Equipped with 3 MB CRAM area.
6ON× Fixed.
7
ON IMX Fixed.
OFF ICS Fixed.
8
ON × CRAM (PA-ME34) mounted.
OFF CRAM (PA-ME34) not mounted.
SWITCH
NAME
SWITCH NO. SETTING
STANDARD
SETTING
MEANING