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RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (T
A = −40 to +85°C)
R01UH0305EJ0200 Rev.2.00 874
Jul 04, 2013
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
HS
Note 1
LS
Note 2
LV
Note 3
Parameter Symbol Conditions
MIN. MAX. MIN. MAX. MIN. MAX.
Unit
16 MHz < fMCK 8/fMCK
−
−
ns 2.7 V ≤ EVDD0 ≤ 3.6 V
f
MCK ≤ 16 MHz 6/fMCK 6/fMCK 6/fMCK ns
2.4 V ≤ EVDD0 ≤ 3.6 V 6/fMCK
and
500ns
6/f
MCK
and
500ns
6/f
MCK
and
500ns
ns
1.8 V ≤ EVDD0 ≤ 3.6 V 6/fMCK
and
750ns
6/f
MCK
and
750ns
6/f
MCK
and
750ns
ns
1.7 V ≤ EVDD0 ≤ 3.6 V 6/fMCK
and
1500ns
6/f
MCK
and
1500ns
6/f
MCK
and
1500ns
ns
SCKp cycle time
Note 4
tKCY2
1.6 V ≤ EV
DD0 ≤ 3.6 V
−
6/fMCK
and
1500ns
6/f
MCK
and
1500ns
ns
2.7 V ≤ EVDD ≤ 3.6 V tKCY2/2
−8
tKCY2/2
−8
tKCY2/2
−8
ns
1.8 V ≤ EVDD0 ≤ 3.6 V tKCY2/2
−18
tKCY2/2
−18
tKCY2/2
−18
ns
1.7 V ≤ EVDD0 ≤ 3.6 V tKCY2/2
−66
tKCY2/2
−66
tKCY2/2
−66
ns
SCKp high-/low-level
width
tKH2,
t
KL2
1.6 V ≤ EV
DD0 ≤ 3.6 V
−
tKCY2/2
−66
tKCY2/2
−66
ns
2.7 V ≤ EVDD0 ≤ 3.6 V 1/fMCK
+20
1/f
MCK
+30
1/f
MCK
+30
ns
1.8 V ≤ EVDD0 ≤ 3.6 V 1/fMCK
+30
1/f
MCK
+30
1/f
MCK
+30
ns
1.7 V ≤ EVDD0 ≤ 3.6 V 1/fMCK
+40
1/f
MCK
+40
1/f
MCK
+40
ns
SIp setup time
(to SCKp↑)
Note 5
t
SIK2
1.6 V ≤ EV
DD0 ≤ 3.6 V
−
1/fMCK
+40
1/f
MCK
+40
ns
1.8 V ≤ EVDD0 ≤ 3.6 V 1/fMCK
+31
1/f
MCK
+31
1/f
MCK
+31
ns
1.7 V ≤ EVDD0 ≤ 3.6 V 1/fMCK+
250
1/fMCK+
250
1/fMCK+
250
ns
SIp hold time
(from SCKp↑)
Note 5
t
KSI2
1.6 V ≤ EV
DD0 ≤ 3.6 V
−
1/fMCK+
250
1/fMCK+
250
ns
2.7 V ≤ EVDD0 ≤ 3.6 V 2/fMCK
+44
2/f
MCK
+110
2/f
MCK
+110
ns
2.4 V ≤ EVDD0 ≤ 3.6 V 2/fMCK
+75
2/f
MCK
+110
2/f
MCK
+110
ns
1.8 V ≤ EVDD0 ≤ 3.6 V 2/fMCK
+110
2/f
MCK
+110
2/f
MCK
+110
ns
1.7 V ≤ EVDD0 ≤ 3.6 V 2/fMCK
+220
2/f
MCK
+220
2/f
MCK
+220
ns
Delay time from SCKp↓
to SOp output
Note 6
t
KSO2 C = 30 pF
Note 7
1.6 V ≤ EV
DD0 ≤ 3.6 V
−
2/fMCK
+220
2/f
MCK
+220
ns
(Note, Caution and Remark are listed on the next page.)