Filter
Top Products
RL78/G1A CHAPTER 28 INSTRUCTION SET
R01UH0305EJ0200 Rev.2.00 845
Jul 04, 2013
Table 28-5. Operation List (13/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (f
CLK) when the code flash memory is accessed, or when the data flash memory is
accessed by an 8-bit instruction.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
ROR A, 1 2 1
−
(CY, A7 ← A0, Am-1 ← Am)×1 ×
ROL A, 1 2 1
−
(CY, A0 ← A7, Am+1 ← Am)×1 ×
RORC A, 1 2 1
−
(CY ← A0, A7 ← CY, Am-1 ← Am)×1 ×
ROLC A, 1 2 1
−
(CY ← A7, A0 ← CY, Am+1 ← Am)×1 ×
AX,1 2 1
−
(CY ← AX15, AX0 ← CY, AXm+1 ← AXm) ×1 ×
Rotate
ROLWC
BC,1 2 1
−
(CY ← BC
15, BC0 ← CY, BCm+1 ← BCm) ×1 ×
CY, A.bit 2 1
−
CY ← A.bit ×
A.bit, CY 2 1
−
A.bit ← CY
CY, PSW.bit 3 1
−
CY ← PSW.bit ×
PSW.bit, CY 3 4
−
PSW.bit ← CY × ×
CY, saddr.bit 3 1
−
CY ← (saddr).bit ×
saddr.bit, CY 3 2
−
(saddr).bit ← CY
CY, sfr.bit 3 1
−
CY ← sfr.bit ×
sfr.bit, CY 3 2
−
sfr.bit ← CY
CY,[HL].bit 2 1 4 CY ← (HL).bit ×
[HL].bit, CY 2 2
−
(HL).bit ← CY
CY, ES:[HL].bit 3 2 5 CY ← (ES, HL).bit ×
MOV1
ES:[HL].bit, CY 3 3
−
(ES, HL).bit ← CY
CY, A.bit 2 1
−
CY ← CY ∧ A.bit ×
CY, PSW.bit 3 1
−
CY ← CY ∧ PSW.bit ×
CY, saddr.bit 3 1
−
CY ← CY ∧ (saddr).bit ×
CY, sfr.bit 3 1
−
CY ← CY ∧ sfr.bit ×
CY,[HL].bit 2 1 4 CY ← CY ∧ (HL).bit ×
AND1
CY, ES:[HL].bit 3 2 5 CY ← CY ∧ (ES, HL).bit ×
CY, A.bit 2 1
−
CY ← CY ∨ A.bit ×
CY, PSW.bit 3 1
−
CYX ← CY ∨ ∨PSW.bit ×
CY, saddr.bit 3 1
−
CY ← CY ∨ (saddr).bit ×
CY, sfr.bit 3 1
−
CY ← CY ∨ sfr.bit ×
CY, [HL].bit 2 1 4 CY ← CY ∨ (HL).bit ×
Bit
manipulate
OR1
CY, ES:[HL].bit 3 2 5 CY ← CY ∨ (ES, HL).bit ×
<R>