Filter
Top Products
RL78/G1A CHAPTER 18 STANDBY FUNCTION
Table 18-2. Operating Statuses in STOP Mode
When STOP Instruction Is Executed While CPU Is Operating on Main System Clock STOP Mode Setting
Item
When CPU Is Operating on
High-speed on-chip oscillator
clock (f
IH)
When CPU Is Operating on
X1 Clock (f
X)
When CPU Is Operating on
External Main System Clock
(f
EX)
System clock Clock supply to the CPU is stopped
fIH
fX
Main system clock
fEX
Stopped
fXT
Subsystem clock
fEXS
Status before STOP mode was set is retained
fIL
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of
subsystem clock supply mode control register (OSMC)
• WUTMMCK0 = 1: Oscillates
• WUTMMCK0 = 0 and WDTON = 0: Stops
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops
CPU
Code flash memory
Operation stopped
Data flash memory Operation stopped
RAM Operation stopped
Port (latch) Status before STOP mode was set is retained
Timer array unit Operation disabled
Real-time clock (RTC)
12-bit interval timer
Operable
Watchdog timer See CHAPTER 10 WATCHDOG TIMER
Clock output/buzzer output
Operates when the subsystem clock is selected as the clock source for counting and the
RTCLPC bit is 0 (operation is disabled when a clock other than the subsystem clock is selected
and the RTCLPC bit is not 0).
A/D converter Wakeup operation is enabled (switching to the SNOOZE mode)
Serial array unit (SAU)
Wakeup operation is enabled only for CSIp and UARTq (switching to the SNOOZE mode)
Operation is disabled for anything other than CSIp and UARTq
Serial interface (IICA)
Wakeup by address match operable
Multiplier and divider/multiply-
accumulator
DMA controller
Operation disabled
Power-on-reset function
Voltage detection function
External interrupt
Key interrupt function
Operable
High-speed CRC
CRC
operation
function
General-purpose
CRC
RAM parity error detection
function
RAM guard function
SFR guard function
Illegal-memory access
detection function
Operation stopped
Remarks 1. Operation stopped: Operation is automatically stopped before switching to the STOP mode.
Operation disabled: Operation is stopped before switching to the STOP mode.
fIH: High-speed on-chip oscillator clock fIL: Low-speed on-chip oscillator clock
f
X: X1 clock fEX: External main system clock
f
XT: XT1 clock fEXS: External subsystem clock
2. p = 00; q = 0
R01UH0305EJ0200 Rev.2.00 733
Jul 04, 2013