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RL78/G1A CHAPTER 19 RESET FUNCTION
19.1 Timing of Reset Operation
This LSI is reset by input of the low level on the RESET pin and released from the reset state by input of the high level
on the RESET pin. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the
operating clock starts.
Figure 19-2. Timing of Reset by RESET Input
Delay
Normal operation
CPU status
Normal operation
(high-speed on-chip oscillator clock)
RESET
Internal reset signal
Port pin
(except P130)
Port pin
(P130)
Note1
High-speed system clock
(when X1 oscillation is selected)
High-speed on-chip
oscillator clock
Reset processing for release from the external reset state
Starting X1 oscillation is specified by software.
Wait for oscillation
accuracy stabilization
Note 2
Note 3
Hi-Z
Reset period
(oscillation
stop)
<R>
<R>
<R>
Release from the reset state is automatic in the case of a reset due to a watchdog timer overflow, execution of an
illegal instruction, a RAM parity error, or an illegal-memory access overflow. After reset processing, execution of the
program with the high-speed on-chip oscillator clock as the operating clock starts.
Figure 19-3. Timing of Reset Due to Execution of Illegal Instruction, Watchdog Timer Overflow, RAM Parity Error,
or Illegal Memory Access Overflow
Note 1
High-speed on-chip
oscillator clock
High-speed system clock
(when X1 oscillation is selected)
CPU status
Watchdog timer overflow/
Execution of illegal instruction/
Detection of RAM parity error/
Detection of illegal memory access
Internal reset signal
Port pin
(except P130)
Port pin
(P130)
Normal operation
Wait for oscillation
accuracy stabilization
Starting X1 oscillation is specified by software
Normal operation
(high-speed on-chip oscillator clock)
0.0511 ms (typ.)
0.0701 ms (max.)
Reset processing
Hi-Z
Reset period
(oscillation stop)
Note 3
<R>
(Notes and Caution are listed on the next page.)
R01UH0305EJ0200 Rev.2.00 742
Jul 04, 2013