Filter
Top Products
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 413
Jul 04, 2013
Figure 12-6. Format of Serial Mode Register mn (SMRmn) (2/2)
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03), After reset: 0020H R/W
F0150H, F0151H (SMR10), F0152H, F0153H (SMR11)
Note 1
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn
CKS
mn
CCS
mn
0 0 0 0 0
STS
mn
Note 2
0
SIS
mn0
Note 2
1 0 0
MD
mn2
MD
mn1
MD
mn0
SIS
mn0
Note 2
Controls inversion of level of receive data of channel n in UART mode
0
Falling edge is detected as the start bit.
The input communication data is captured as is.
1
Rising edge is detected as the start bit.
The input communication data is inverted and captured.
MD
mn2
MD
mn1
Setting of operation mode of channel n
0 0 CSI mode
0 1 UART mode
1 0 Simplified I
2
C mode
1 1 Setting prohibited
MD
mn0
Selection of interrupt source of channel n
0 Transfer end interrupt
1 Buffer empty interrupt
(Occurs when data is transferred from the SDRmn register to the shift register.)
For successive transmission, the next transmit data is written by setting the MDmn0 bit to 1 when SDRmn data has
run out.
Notes 1. SMR00 to SMR03: All products
SMR10, SMR11: 32, 48, and 64-pin products
2. The SMR01, SMR03, and SMR11 registers only.
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 (or bits 13 to 6, 4, and 3 for the SMR00, SMR02, or SMR10
register) to “0”. Be sure to set bit 5 to “1”.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21),
q: UART number (q = 0 to 2), r: IIC number (r = 00, 01, 10, 11, 20, 21)
12.3.4 Serial communication operation setting register mn (SCRmn)
The SCRmn register is a communication operation setting register of channel n. It is used to set a data
transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit, start bit,
stop bit, and data length.
Rewriting the SCRmn register is prohibited when the register is in operation (when SEmn = 1).
The SCRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets the SCRmn register to 0087H.
<R>