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RL78/G1A CHAPTER 11 A/D CONVERTER
R01UH0305EJ0200 Rev.2.00 372
Jul 04, 2013
11.6 A/D Converter Operation Modes
The operation of each A/D converter mode is described below. In addition, the procedure for specifying each mode is
described in 11.7 A/D Converter Setup Flowchart.
11.6.1 Software trigger mode (select mode, sequential conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> After the software counts up to the stabilization wait time
Note
, the ADCS bit of the ADM0 register is set to 1 to
perform the A/D conversion of the analog input specified by the analog input channel specification register (ADS).
<3> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next
A/D conversion immediately starts.
<4> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
<5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
<6> Even if a hardware trigger is input during conversion operation, A/D conversion does not start.
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status.
<8> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status.
When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start.
Note If a high-accuracy channel is selected as the analog input channel: Stabilization wait time = 0.5
μ
s
If a standard channel is selected as the analog input channel: Stabilization wait time = 2
μ
s
Figure 11-17. Example of Software Trigger Mode (Select Mode, Sequential Conversion Mode) Operation Timing
ADCE
ADCS
ADS
INTAD
ADCR,
ADCRH
A/D
conversion
status
ANI0 ANI1
Data 6
(ANI1)
Data 7
(ANI1)
Data 6
(ANI1)
Data 7
(ANI1)
Data 8
(ANI1)
Data 1
(ANI0)
Data 1
(ANI0)
Data 2
(ANI0)
Data 4
(ANI0)
Data 2
(ANI0)
Data 3
(ANI0)
Data 4
(ANI0)
Data 5
(ANI0)
The trigger
is not
acknowledged.
The trigger
is not
acknowledged.
Conversion
standby
Conversion
standby
Stop
status
Stop
status
A/D conversion
ends and the next
conversion starts.
Conversion is
interrupted.
ADS is rewritten during
A/D conversion operation
(from ANI0 to ANI1).
ADCS is set to 1 while in the
conversion standby status.
ADCS is overwritten
with 1 during A/D
conversion operation.
ADCE is set to 1.
<3> <3> <3>
Conversion is
interrupted
and restarts.
<3>
<4>
A hardware trigger
is generated
(and ignored).
<6>
<5>
<2>
ADCS is cleared to
0 during A/D
conversion operation.
<7>
<1>
ADCE is cleared to 0.
<8>
<3>