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RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 478
Jul 04, 2013
(1) Register setting
Figure 12-56. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI10, CSI11, CSI20, CSI21)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn
CKSmn
0/1
CCSmn
1
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
0
MDmn1
0
MDmn0
0
Operation clock (fMCK) of channel n
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
Interrupt source of channel n
0: Transfer end interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn
TXEmn
0
RXEmn
1
DAPmn
0/1
CKPmn
0/1
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0/1
0
SLCmn1
0
SLCmn0
0
0
1
DLSmn1
1
Note 1
DLSmn0
0/1
Selection of the data and clock
phase (For details about the
setting, see 12.3 Registers
Controlling Serial Array Unit.)
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
Setting of data length
0: 7-bit data length
1: 8-bit data length
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
0000000
Baud rate setting
0
Receive data
(d) Serial output register m (SOm) …The Register that not used in this mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
CKOm3
Note 2
×
CKOm2
Note 2
×
CKOm1
×
CKOm0
×
0
0
0
0
SOm3
Note 2
×
SOm2
Note 2
×
SOm1
×
SOm0
×
Notes 1. Only provided for the SCR00 and SCR01 registers. This bit is fixed to 1 for the other registers.
2. Unit 0 only
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
p: CSI number (p = 00, 01, 10, 11, 20, 21), mn = 00 to 03, 10, 11
2. : Setting is fixed in the CSI slave transmission mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOp