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RL78/G1A CHAPTER 5 CLOCK GENERATOR
R01UH0305EJ0200 Rev.2.00 177
Jul 04, 2013
5.6.7 Conditions before clock oscillation is stopped
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
conditions before the clock oscillation is stopped.
Table 5-7. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Clock
Conditions Before Clock Oscillation Is Stopped
(External Clock Input Disabled)
Flag Settings of SFR
Register
High-speed on-chip
oscillator clock
MCS = 1 or CLS = 1
(The CPU is operating on a clock other than the high-speed on-chip
oscillator clock.)
HIOSTOP = 1
X1 clock
External main system clock
MCS = 0 or CLS = 1
(The CPU is operating on a clock other than the high-speed system clock.)
MSTOP = 1
XT1 clock
External subsystem clock
CLS = 0
(The CPU is operating on a clock other than the subsystem clock.)
XTSTOP = 1