Renesas rl78 Answering Machine User Manual


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RL78/G1A CHAPTER 1 OUTLINE
1.3.4 64-pin products
64-pin plastic LFQFP (10 × 10 mm, 0.5 mm pitch)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P27/ANI7
P26/ANI6/(KR9)
P25/ANI5/(KR8)
P24/ANI4/(KR7)
P23/ANI3/(KR6)
P22/ANI2/(KR5)
P21/ANI1/AV
REFM
P20/ANI0/AV
REFP
P130
P04/SCK10/SCL10/(KR4)
P03/ANI16/SI10/SDA10/RxD1/(KR3)
P02/ANI17/SO10/TxD1/(KR2)
P01/TO00/(KR1)
P00/TI00/(KR0)
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
P30/ANI27/SCK11/SCL11/INTP3/RTC1HZ
P05/TI05/TO05/KR8
P06/TI06/TO06/KR9
P70/ANI28/SCK21/SCL21/KR0
P71/SI21/SDA21/KR1
P72/SO21/KR2
P73/SO01/KR3
P74/SI01/SDA01/INTP8/KR4
P75/SCK01/SCL01/INTP9/KR5
P76/INTP10/KR6
P77/INTP11/KR7
P31/ANI29/TI03/TO03/INTP4
P63
P62
P61/SDAA0
P60/SCLA0
AV
SS
AV
DD
P150/ANI8
P151/ANI9/(KR6)
P152/ANI10/(KR7)
P153/ANI11/(KR8)
P154/ANI12/(KR9)
P10/ANI18/SCK00/SCL00/(KR0)
P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1)
P12/ANI21/SO00/TxD0/TOOLTxD/(KR2)
P13/ANI22/SO20/TxD2/(KR3)
P14/ANI23/SI20/SDA20/RxD2/(KR4)
P15/ANI24/SCK20/SCL20/(KR5)
P16/TI01/TO01/INTP5
P51/ANI25/SO11/INTP2
P50/ANI26/SI11/SDA11/INTP1
P120/ANI19
P43
P42/TI04/TO04
P41/ANI30/TI07/TO07
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
V
SS
EV
SS0
V
DD
EV
DD0
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Cautions 1. Make EVSS0 pin the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD0 pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the V
DD and EVDD0 pins and connect
the V
SS and EVSS0pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).
R01UH0305EJ0200 Rev.2.00 10
Jul 04, 2013