Renesas rl78 Answering Machine User Manual


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RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA
13.3 Registers Controlling Serial Interface IICA
Serial interface IICA0 is controlled by the following registers.
• Peripheral enable register 0 (PER0)
• IICA control register 00 (IICCTL00)
• IICA flag register 0 (IICF0)
• IICA status register 0 (IICS0)
• IICA control register 01 (IICCTL01)
• IICA low-level width setting register 0 (IICWL0)
• IICA high-level width setting register 0 (IICWH0)
• Port mode register 6 (PM6)
• Port register 6 (P6)
13.3.1 Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware
macro that is not used is stopped in order to reduce the power consumption and noise.
When serial interface IICA0 is used, be sure to set bit 4 (IICA0EN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13-5. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
Jul 04, 2013
PER0 RTCEN 0 ADCEN IICA0EN SAU1EN
Note
SAU0EN 0 TAU0EN
IICA0EN Control of serial interface IICA0 input clock supply
Stops input clock supply.
0
SFR used by serial interface IICA0 cannot be written.
Serial interface IICA0 is in the reset status.
Enables input clock supply.
1
SFR used by serial interface IICA0 can be read/written.
Note 32-, 48-, and 64-pin products only.
Cautions 1. When setting serial interface IICA0, be sure to set the following registers first while the
IICA0EN bit is set to 1. If IICA0EN = 0, the control registers of serial interface IICA are set to
their initial values, and writing to them is ignored (except for port mode register 6 (PM6) and
port register 6 (P6)).
• IICA control register 00 (IICCTL00)
• IICA flag register 0 (IICF0)
• IICA status register 0 (IICS0)
• IICA control register 01 (IICCTL01)
• IICA low-level width setting register 0 (IICWL0)
• IICA high-level width setting register 0 (IICWH0)
2. Be sure to clear the following bits to 0.
25-pin products: bits 1, 3, 6
32-, 48-, 64-pin products: bits 1, 6
R01UH0305EJ0200 Rev.2.00 572