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RL78/G1A CHAPTER 3 CPU ARCHITECTURE
R01UH0305EJ0200 Rev.2.00 51
Jul 04, 2013
Figure 3-4. Memory Map (R5F10ExE (x = 8, B, G, L))
00000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
FEEFFH
FEF00H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFFFFH
00000H
0007FH
00080H
000BFH
000C0H
000C3H
000C4H
00FFFH
01000H
0107FH
01080H
010BFH
010C0H
010C3H
010C4H
0FFFFH
0FFFFH
10000H
Special function register (SFR)
256 bytes
RAM
Notes 1, 2
4 KB
General-purpose register
32 bytes
Code flash memory
64 KB
Special function register (2nd SFR)
2 KB
Mirror
51.75 KB
Vector table area
128 bytes
CALLT table area
64 bytes
Program area
Option byte area
Note 3
4 bytes
Vector table area
128 bytes
CALLT table area
64 bytes
Option byte area
Note 3
4 bytes
Program area
Reserved
Reserved
Program
memory
space
Data memory
space
On-chip debug security
ID setting area
Note 3
10 bytes
01FFFH
Boot cluster 0
Note 4
Boot cluster 1
010CDH
010CEH
On-chip debug security
ID setting area
Note 3
10 bytes
000CDH
000CEH
Data flash memory
4 KB
F1FFFH
F2000H
Notes 1. During self programming and data flash rewriting, the stack, data buffer, and RAM addresses used as
branch destinations for vectored interrupts or as sources or destinations of DMA transfers must not be
allocated to the area between addresses FFE20H and FFEDFH. Also, use of the area FEF00H to FF309H
is prohibited, because this area is used for each library.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.7 Security Setting).
Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data
access is to proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas,
respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details,
see 22.3.3 RAM parity error detection function.