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RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION
The operation when a valid edge is input to multiple key interrupt input pins is shown in Figure 17-10 below. A falling
edge is also input to the KR1 and KR6 pins after a falling edge was input to the KR0 pin (when KREG = 0). The KRF1 bit
is set when the KRF0 bit is cleared. A key interrupt (INTKR) is therefore generated one clock (f
CLK) after the KRF0 bit is
cleared (<1> in the figure). Also, after a falling edge has been input to the KR6 pin, a low level continues to be input to this
pin (<3> in the figure) until the KRF1 bit is cleared (<2> in the figure). A key interrupt (INTKR) is therefore generated one
clock (f
CLK) after the KRF1 bit is cleared (<4> in the figure). It is thus possible to generate a key interrupt (INTKR) when a
valid edge is input to multiple channels.
Figure 17-10. Operation of INTKR Signal When Key Interrupts Are Input to Multiple Channels
(When KRMD = 1 and KREG = 0)
KR0
KR1
KR6
<3>
KRF0
<2>
KRF1
<1>
INTKR
KRIF
Note 1
Note 2
Delay
time
Note 1
Delay
time
Note 2 Note 2
Clear Clear
<4>
Delay
time
Cleared by software
Cleared by software
Note 1
Notes 1. The maximum delay time is the maximum value of the high-level width and low-level width of the key
interrupt input (see 29.4 AC Characteristics and 30.4 AC Characteristics for details).
2. Acknowledgment of vectored interrupt request or bit cleared by software
Remark f
CLK: CPU/peripheral hardware clock frequency
R01UH0305EJ0200 Rev.2.00 724
Jul 04, 2013