Filter
Top Products
61
CHAPTER 3 CPU
3.7.4 Standby Control Register (STBC)
The standby control register (STBC) controls the CPU to enter to sleep mode, stop
mode, sets the pin states in stop mode, and initiates software reset.
■ Standby control register (STBC)
Figure 3.7-1 Standby control register (STBC)
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value
0008
H
STP SLP SPL RST ————0001----
B
WWR/WW
RST
Software reset bit
Read Write
0 —
Generates a reset signal for
four instruction cycles.
1 Reading always returns “1”. No effect on operation.
SPL Pin state specification bit
0
External pins hold their states prior to entering stop mode.
1
External pins go to high-impedance state on entering stop
SLP
Sleep bit
Read Write
0 Reading always returns “0”. No effect on operation.
1 — Goes to sleep mode.
STP
Stop bit
Read Write
0 Reading always returns “0”. No effect on operation.
1 — Goes to stop mode.
R/W : Readable and writable
W : Write-only
— : Unused
X : Indeterminate
: Initial value
mode.