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CHAPTER 9 8-BIT SERIAL I/O
Figure 9.7-3 Operation during halt (internal shift clock)
■ Using external shift clock
●
Operation in sleep mode
In sleep mode, serial I/O operation does not halt and transfer continues, as shown in Figure 9.7-4
"Operation in sleep mode (external shift clock)".
Figure 9.7-4 Operation in sleep mode (external shift clock)
●
Operation in stop mode
In stop mode, serial I/O operation halts and transfer aborts, as shown in Figure 9.7-5 "Operation in stop
mode (external shift clock)". Operation restarts after wake-up from stop mode. This causes an error to
occur on the device with which the 8-bit serial I/O is communicating. Initialize the 8-bit serial I/O after
wake-up from stop mode.
#0 #1 #2 #3 #4 #5 #0 #1
SCK output
SST bit
SIOF bit
SO pin output
Operation halts.
Reset SDR register
Operation reactivates.
#0 #1 #2 #3 #4 #5 #6 #7
SCK input
Clock for next data
SST bit
Transfer disable state
SIOF bit
Cleared by the program.
SO pin output
Sleep mode
SLP bit
Wake-up from sleep mode by IRQ5
(STBC register)