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CHAPTER 3 CPU
3.4 Interrupts
The MB89950/950A series has 12 interrupt request inputs corresponding to peripheral
functions. The interrupt level can be set independently.
If an interrupt request output is enabled in the peripheral function, an interrupt request
from a peripheral function is compared with the interrupt level in the interrupt
controller. The CPU performs interrupt operation according to how the interrupt is
accepted. The CPU wakes up from standby mode, and returns to the interrupt or normal
operation.
■ Interrupt requests from peripheral functions
Table 3.4-1 "Interrupt request and interrupt vector" lists the interrupt requests corresponding to the
peripheral functions. On acceptance of an interrupt, execution branches to the interrupt processing routine.
The contents of interrupt the vector table address corresponding to the interrupt request specifies the branch
destination address for the interrupt processing routine.
An interrupt processing level can be for each interrupt request in the interrupt level setting registers (ILR1,
ILR2, ILR3). Three levels are available.
If an interrupt request with the same or lower level occurs during execution of an interrupt processing
routine, the latter interrupt is not normally processed until the current interrupt processing routine
completes. If interrupt request set the same level occur simultaneously, the highest priority is IRQ0.
Table 3.4-1 Interrupt request and interrupt vector
Interrupt request
Vector table address Bit names of the
interrupt level
setting register
Priority
(*1)
Upper Lower
IRQ0 (External interrupt 0)
FFFA
H
FFFB
H
L01, L00
IRQ1 (External interrupt 1)
FFF8
H
FFF9
H
L11, L10
IRQ2 (8-bit PWM timer)
FFF6
H
FFF7
H
L21, L20
IRQ3 (PWC)
FFF4
H
FFF5
H
L31, L30
IRQ4 (UART)
FFF2
H
FFF3
H
L41, L40
IRQ5 (8-bit serial I/O)
FFF0
H
FFF1
H
L51, L50
IRQ6 (Timebase timer)
FFEE
H
FFEF
H
L61, L60
IRQ7 (Unused)
FFEC
H
FFED
H
L71, L70
IRQ8 (Unused)
FFEA
H
FFEB
H
L81, L80
IRQ9 (Unused)
FFE8
H
FFE9
H
L91, L90
IRQA (Unused)
FFE6
H
FFE7
H
LA1,LA0
IRQB (Unused)
FFE4
H
FFE5
H
LB1, LB0
*1: This priority is applied when interrupts of the same level occur simultaneously.
High
Low