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CHAPTER 9 8-BIT SERIAL I/O
Figure 9.7-5 Operation in stop mode (external shift clock)
●
Operation during halt
Halting operation during transfer (SMR: SST = "0") halts the transfer and clears the shift clock counter, as
shown in Figure 9.7-6 "Operation during halt (external shift clock)". Therefore, the device being
communicated with must also be initialized. In serial output operation, set the SDR register again before re-
activating. If an external clock is input at this time, the SO pin output changes.
Figure 9.7-6 Operation during halt (external shift clock)
#0 #1 #2 #3 #4 #5 #6 #7
Stop request
Oscillation
stabilization
delay time
Interrupt request
Transfer error occurs
Wake-up from stop mode by an external interrupt.
SCK input
SST bit
SIOF bit
SO pin output
STP bit
Stop mode
Clock for next data
Cleared by the program.
#6
#7
(STBC register)
#0 #1 #2 #3 #4 #5 #0 #1
#6 #7
SCK input
SST bit
SIOF bit
SO pin output
Clock for next data
Operation halts
Reset SDR register
Operation reactivates