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CHAPTER 9 8-BIT SERIAL I/O
Bit 0 SST:
Serial I/O transfer
start bit
• This bit controls serial I/O transfer start and transfer enable. This bit can also be used to determine
whether transfer has completed.
• Writing "1" to this bit when an internal shift clock is selected (CKS1, CKS0 = other than "11
B
")
clears the shift clock counter and starts data transfer.
• Writing "1" to this bit when an external shift clock is selected (CKS1, CKS0 = "11
B
") enables data
transfer, clears the shift clock counter, and sets serial I/O to delay for input of the external shift
clock.
• This bit is cleared to "0" and the SIOF bit is set to "1" when transfer completes.
• Writing "0" to this bit while transfer is in progress (SST = "1") aborts the transfer.
After halting a transfer, data must be set again to the SDR register for data output and transfer
restarted (the shift clock counter cleared) for data input.
Table 9.3-1 Serial mode register (SMR) bits
Bit Function