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1745D–ATARM–04-Nov-05
AT91M55800A
15.4 Interrupt Masking
Each interrupt source, including FIQ, can be enabled or disabled using the command registers
AIC_IECR and AIC_IDCR. The interrupt mask can be read in the Read-only register AIC_IMR.
A disabled interrupt does not affect the servicing of other interrupts.
15.5 Interrupt Clearing and Setting
All interrupt sources which are programmed to be edge-triggered (including FIQ) can be indi-
vidually set or cleared by respectively writing to the registers AIC_ISCR and AIC_ICCR. This
function of the interrupt controller is available for auto-test or software debug purposes.
15.6 Fast Interrupt Request
The external FIQ line is the only source which can raise a fast interrupt request to the proces-
sor. Therefore, it has no priority controller.
The external FIQ line can be programmed to be positive or negative edge-triggered or high- or
low-level sensitive in the AIC_SMR0 register.
The fast interrupt handler address can be stored in the AIC_SVR0 register. The value written
into this register is available by reading the AIC_FVR register when an FIQ interrupt is raised.
By storing the following instruction at address 0x0000001C, the processor loads the program
counter with the interrupt handler address stored in the AIC_FVR register.
ldr PC,[PC,# -&F20]
Alternatively, the interrupt handler can be stored starting from address 0x0000001C as
described in the ARM7TDMI datasheet.
15.7 Software Interrupt
Interrupt source 1 of the advanced interrupt controller is a software interrupt. It must be pro-
grammed to be edge-triggered in order to set or clear it by writing to the AIC_ISCR and
AIC_ICCR.
This is totally independent of the SWI instruction of the ARM7TDMI processor.
15.8 Spurious Interrupt
When the AIC asserts the NIRQ line, the ARM7TDMI enters IRQ mode and the interrupt han-
dler reads the IVR. It may happen that the AIC de-asserts the NIRQ line after the core has
taken into account the NIRQ assertion and before the read of the IVR.
This behavior is called a Spurious Interrupt.
The AIC is able to detect these Spurious Interrupts and returns the Spurious Vector when the
IVR is read. The Spurious Vector can be programmed by the user when the vector table is
initialized.
A Spurious Interrupt may occur in the following cases:
• With any sources programmed to be level sensitive, if the interrupt signal of the AIC input is
de-asserted at the same time as it is taken into account by the ARM7TDMI.
• If an interrupt is asserted at the same time as the software is disabling the corresponding
source through AIC_IDCR (this can happen due to the pipelining of the ARM Core).