45
1745D–ATARM–04-Nov-05
AT91M55800A
Figure 11-23. 1 Wait State, 8-bit Bus Width, Half-word Transfer
ADDR
X B
1
1 Wait State
MCK
A0 - A23
NCS
NRD
D0 - D15
Internal Bus
ADDR+1
1 Wait State
X X B
2
B
1
X B
2
X X X B
1
READ ACCESS
· Standard Protocol
· Early Protocol
NRD
X B
1
D0 - D15
X B
2
WRITE ACCESS
NWR0
X B
1
D0 - D15
X B
2
NWR1