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1745D–ATARM–04-Nov-05
AT91M55800A
16.9 PIO User Interface
PIO Controller A Base Address:0xFFFEC000 (Code Label PIOA_BASE)
PIO Controller B Base Address:0xFFFF0000 (Code Label PIOB_BASE)
Notes: 1. The reset value of this register depends on the level of the external pins at reset.
2. This register is cleared at reset. However, the first read of the register can give a value not equal to zero if any changes have
occurred on any pins between the reset and the read.
Table 16-3. PIO Controller Memory Map
Offset Register Name Access Reset State
0x00 PIO Enable Register PIO_PER Write-only –
0x04 PIO Disable Register PIO_PDR Write-only –
0x08
PIO Status Register
PIO_PSR Read-only
0x3FFF FFFF (A)
0x0FFF FFFF (B)
0x0C Reserved – – –
0x10 Output Enable Register PIO_OER Write-only –
0x14 Output Disable Register PIO_ODR Write-only –
0x18 Output Status Register PIO_OSR Read-only 0
0x1C Reserved – – –
0x20 Input Filter Enable Register PIO_IFER Write-only –
0x24 Input Filter Disable Register PIO_IFDR Write-only –
0x28 Input Filter Status Register PIO_IFSR Read-only 0
0x2C Reserved – – –
0x30 Set Output Data Register PIO_SODR Write-only –
0x34 Clear Output Data Register PIO_CODR Write-only –
0x38 Output Data Status Register PIO_ODSR Read-only 0
0x3C Pin Data Status Register PIO_PDSR Read-only see Note
(1)
0x40 Interrupt Enable Register PIO_IER Write-only –
0x44 Interrupt Disable Register PIO_IDR Write-only –
0x48 Interrupt Mask Register PIO_IMR Read-only 0
0x4C Interrupt Status Register PIO_ISR Read-only see Note
(2)
0x50 Multi-driver Enable Register PIO_MDER Write-only –
0x54 Multi-driver Disable Register PIO_MDDR Write-only –
0x58 Multi-driver Status Register PIO_MDSR Read-only 0
0x5C Reserved – – –