111
1745D–ATARM–04-Nov-05
AT91M55800A
masking or unmasking the interrupts depending on the state saved in the SPSR (the
previous state of the ARM Core).
Note: The I bit in the SPSR is significant. If it is set, it indicates that the ARM Core was just about to
mask IRQ interrupts when the mask instruction was interrupted. Hence, when the SPSR is
restored, the mask instruction is completed (IRQ is masked).