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1745D–ATARM–04-Nov-05
AT91M55800A
20.7 SPI Programmer’s Model
SPI Base Address: 0xFFFBC000 (Code Label SPI_BASE)
Table 20-1. SPI Memory Map
Offset Register Name Access Reset State
0x00 Control Register SP_CR Write-only –
0x04 Mode Register SP_MR Read/Write 0
0x08 Receive Data Register SP_RDR Read-only 0
0x0C Transmit Data Register SP_TDR Write-only –
0x10 Status Register SP_SR Read-only 0
0x14 Interrupt Enable Register SP_IER Write-only –
0x18 Interrupt Disable Register SP_IDR Write-only –
0x1C Interrupt Mask Register SP_IMR Read-only 0
0x20 Receive Pointer Register SP_RPR Read/Write 0
0x24 Receive Counter Register SP_RCR Read/Write 0
0x28 Transmit Pointer Register SP_TPR Read/Write 0
0x2C Transmit Counter Register SP_TCR Read/Write 0
0x30 Chip Select Register 0 SP_CSR0 Read/Write 0
0x34 Chip Select Register 1 SP_CSR1 Read/Write 0
0x38 Chip Select Register 2 SP_CSR2 Read/Write 0
0x3C Chip Select Register 3 SP_CSR3 Read/Write 0