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1745D–ATARM–04-Nov-05
AT91M55800A
14.0.5 WD Status Register
Name: WD_SR
Access: Read-only
Reset Value: 0x0
Offset: 0x0C
• WDOVF: Watchdog Overflow (Code Label WD_WDOVF)
0 = No watchdog overflow.
1 = A watchdog overflow has occurred since the last restart of the watchdog counter or since internal or external reset.
14.0.6 WD Enabling Sequence
To enable the Watchdog Timer, the sequence is as follows:
1. Disable the Watchdog by clearing the bit WDEN:
Write 0x2340 to WD_OMR
This step is unnecessary if the WD is already disabled (reset state).
2. Initialize the WD Clock Mode Register:
3. Write 0x373C to WD_CMR
(HPCV = 15 and WDCLKS = MCK/8)
4. Restart the timer: Write 0xC071 to WD_CR
5. Enable the watchdog:
Write 0x2345 to WD_OMR (interrupt enabled)
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WDOVF