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1745D–ATARM–04-Nov-05
AT91M55800A
Figure 11-19 through Figure 11-25 show the timing cycles and wait states for read and write
access to the various AT91M55800A external memory devices. The configurations described
are as follows:
Table 11-1. Memory Access Waveforms
Figure Number Number of Wait States Bus Width Size of Data Transfer
11-19 0 16 Word
11-20 1 16 Word
11-21 1 16 Half-word
11-22 0 8 Word
11-23 1 8 Half-word
11-24 1 8 Byte
11-25 0 16 Byte