37
1745D–ATARM–04-Nov-05
AT91M55800A
Figure 11-16. Early Read Protocol with no t
DF
Read
Mem 1
Write
Mem 1
A0 - A23
NRD
NWE
NCS1
NCS2
D0 - D15 (Mem 1)
D0 - D15 (Mem 2)
D0 - D15 (AT91)
MCK
Early Read
Wait Cycle
Read
Mem 1
Read
Mem 2
Write
Mem 2
Early Read
Wait Cycle
Read
Mem 2
Chip Select
Change Wait
Long t
WHDX
Long t
WHDX