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1745D–ATARM–04-Nov-05
AT91M55800A
15.1 Hardware Interrupt Vectoring
The hardware interrupt vectoring reduces the number of instructions to reach the interrupt
handler to only one. By storing the following instruction at address 0x00000018, the processor
loads the program counter with the interrupt handler address stored in the AIC_IVR register.
Execution is then vectored to the interrupt handler corresponding to the current interrupt.
ldr PC,[PC,# -&F20]
The current interrupt is the interrupt with the highest priority when the Interrupt Vector Register
(AIC_IVR) is read. The value read in the AIC_IVR corresponds to the address stored in the
Source Vector Register (AIC_SVR) of the current interrupt. Each interrupt source has its cor-
responding AIC_SVR. In order to take advantage of the hardware interrupt vectoring it is
necessary to store the address of each interrupt handler in the corresponding AIC_SVR, at
system initialization.
15.2 Priority Controller
The NIRQ line is controlled by an 8-level priority encoder. Each source has a programmable
priority level of 7 to 0. Level 7 is the highest priority and level 0 the lowest.
When the AIC receives more than one unmasked interrupt at a time, the interrupt with the
highest priority is serviced first. If both interrupts have equal priority, the interrupt with the low-
est interrupt source number (see Table Table 15-1) is serviced first.
The current priority level is defined as the priority level of the current interrupt at the time the
register AIC_IVR is read (the interrupt which is serviced).
In the case when a higher priority unmasked interrupt occurs while an interrupt already exists,
there are two possible outcomes depending on whether the AIC_IVR has been read.
• If the NIRQ line has been asserted but the AIC_IVR has not been read, then the processor
reads the new higher priority interrupt handler address in the AIC_IVR register and the
current interrupt level is updated.
• If the processor has already read the AIC_IVR then the NIRQ line is reasserted. When the
processor has authorized nested interrupts to occur and reads the AIC_IVR again, it reads
the new, higher priority interrupt handler address. At the same time the current priority
value is pushed onto a first-in last-out stack and the current priority is updated to the higher
priority.
When the end of interrupt command register (AIC_EOICR) is written the current interrupt level
is updated with the last stored interrupt level from the stack (if any). Hence at the end of a
higher priority interrupt, the AIC returns to the previous state corresponding to the preceding
lower priority interrupt which had been interrupted.
15.3 Interrupt Handling
The interrupt handler must read the AIC_IVR as soon as possible. This de-asserts the NIRQ
request to the processor and clears the interrupt in case it is programmed to be edge-trig-
gered. This permits the AIC to assert the NIRQ line again when a higher priority unmasked
interrupt occurs.
At the end of the interrupt service routine, the end of interrupt command register (AIC_EOICR)
must be written. This allows pending interrupts to be serviced.