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1745D–ATARM–04-Nov-05
AT91M55800A
18.3.2 Synchronous Receiver
When configured for synchronous operation (SYNC = 1), the receiver samples the RXD signal
on each rising edge of the Baud Rate clock. If a low level is detected, it is considered as a
start. Data bits, parity bit and stop bit are sampled and the receiver waits for the next start bit.
See example in Figure 18-5.
Figure 18-5. Synchronous Mode: Character Reception
18.3.3 Receiver Ready
When a complete character is received, it is transferred to the US_RHR and the RXRDY sta-
tus bit in US_CSR is set. If US_RHR has not been read since the last transfer, the OVRE
status bit in US_CSR is set.
18.3.4 Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits,
in accordance with the field PAR in US_MR. It then compares the result with the received par-
ity bit. If different, the parity error bit PARE in US_CSR is set. When the character is
completed and as soon as the character is read, the parity status bit is cleared.
18.3.5 Framing Error
If a character is received with a stop bit at low level and with at least one data bit at high level,
a framing error is generated. This sets FRAME in US_CSR.
18.3.6 Time-out
This function allows an idle condition on the RXD line to be detected. The maximum delay for
which the USART should wait for a new character to arrive while the RXD line is inactive (high
level) is programmed in US_RTOR (Receiver Time-out). When this register is set to 0, no
time-out is detected. Otherwise, the receiver waits for a first character and then initializes a
counter which is decremented at each bit period and reloaded at each byte reception. When
the counter reaches 0, the TIMEOUT bit in US_CSR is set. The user can restart the wait for a
first character with the STTTO (Start Time-out) bit in US_CR.
Calculation of time-out duration:
D0 D1 D2 D3 D4 D5 D6 D7
RXD
True Start Detection
Sampling
Parity Bit
Stop Bit
Example: 8-bit, parity enabled 1 stop
SCK
Duration Value 4 BitPeriod••=