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1745D–ATARM–04-Nov-05
AT91M55800A
12. APMC: Advanced Power Management Controller
The AT91M55800A features an Advanced Power Management Controller, which optimizes
both the power consumption of the device and the complete system. The APMC controls the
clocking elements such as the oscillators and the PLL, the core and the peripheral clocks, and
has the capability to control the system power supply.
Main Power is used throughout this document to identify the voltages powering the
AT91M55800A and other components of the system, with the exception of the Battery Backup
voltage, which is applied to the VDDBU. Main Power supplies VDDIO, VDDCORE and, if
required, the analog voltage VDDA. A battery or battery capacitor generally supplies the Bat-
tery Backup Power.
The APMC consists of the following elements:
• The RTC Oscillator, which provides the Slow Clock at 32768 Hz.
• The Main Oscillator, which provides a clock that depends on the frequency of the crystal
connected to the XIN and XOUT pins.
• The Phase Lock Loop.
• The ARM Core Clock Controller, which allows entry to the Idle Mode.
• The Peripheral Clock Controller, which conserves the power consumption of unused
peripherals.
• The Master Clock Output Controller.
• The Shut-down Logic, which controls the Main Power.
Figure 12-1. APMC Module
Note: The RTC peripheral is described in a separate section.
Advanced Peripheral Bus
IRQ
Control
PLL TimerOSC Timer
PLL Main OSC
Device
Clock
Control
RTC
(1)
RTC
OSC
Reset Control
Shut-down
Logic
APMC
VDDIO/VDDCORE
VDDBU
WAKEUP
NRSTBU
XIN32
XOUT32
XIN
XOUT
SHDN
APMCIRQ
Arm Clock
Peripheral Clocks
0
ARM Interrupt (IRQ and FIQ)
n
Alarm
SLCKIRQ
Slow Clock_SLCK