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1745D–ATARM–04-Nov-05
AT91M55800A
• CSS: Clock Source Selection
• OSCOUNT: Main Oscillator Counter
Specifies the number of 32,768 Hz divided by 8 clock cycles for the main oscillator start-up timer to count before the main
oscillator is stabilized, after the oscillator is enabled. The main oscillator counter is a down-counter which is preloaded with
the OSCOUNT value when the MOSCEN bit in the Clock Generator Mode register (CGMR) is set, but only if the
OSCOUNT value is different from 0x0.
• PLLCOUNT: PLL Lock Counter
Specifies the number of 32,768 Hz clock cycles for the PLL lock timer to count before the PLL is locked, after the PLL is
started. The PLL counter is a down-counter which is preloaded with the PLLCOUNT value when the MUL field in the Clock
Generator Mode register (CGMR) is modified, but only if the MUL value is different from 0 (PLL disabled) and also the
PLLCOUNT value itself different from 0x0. PLLCOUNT must be loaded with a minimum value of 2 in order to guarantee a
time of at least one slow clock period.
CSS Clock Source Selection Code Label
0 0 Low-frequency clock provided by the RTC APMC_CSS_LF
0 1 Main oscillator Output or external clock APMC_CSS_MOSC
1 0 Phase Lock Loop Output APMC_CSS_PLL
1 1 Reserved –