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1745D–ATARM–04-Nov-05
AT91M55800A
In other cases, the following erroneous behavior occurs:
– 32-bit read accesses are not managed correctly and the first 16-bit data sampling
takes into account only the standard wait states. 16- and 8-bit accesses are not
affected.
– During write accesses of any type, the NWE rises on the rising edge of the last
cycle as defined by the programmed number of wait states. However, NWAIT
assertion does affect the length of the total access. Only the NWE pulse length is
inaccurate.
At maximum speed, asserting the NWAIT in the first access cycle is not possible, as the sum
of the timings “MCKI Falling to Chip Select” and “NWAIT setup to MCKI rising” are generally
higher than one half of a clock period. This leads to using at least one standard wait state.
However, this is not sufficient except to perform byte or half-word read accesses. Word and
write accesses require at least two standard wait states.
The following waveforms further explain the issue:
If the NWAIT setup time is satisfied on the first rising edge of MCKI, the behavior is accurate.
The EBI operations are not affected when the NWAIT rises.
Figure 27-1. NWAIT Rising
If the NWAIT setup time is satisfied on the following edges of MCKI and if at least one stan-
dard wait state remains to be executed, the behavior is accurate. In the following example, the
number of standard wait states is two. The NWAIT setup time on the second rising edge of
MCKI must be met.
NWAIT Setup before MCKI Rising (EBI
5
)
MCKI
NWAIT