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1745D–ATARM–04-Nov-05
AT91M55800A
Figure 27-2. Number of Standard Wait States is Two
Note: 1. These numbers refer to the standard access cycles.
If the first two conditions are not met during a 32-bit read access, the first 16-bit data is read at
the end of the standard 16-bit read access. In the following example, the number of standard
waits is one. NWAIT assertions do affect both NRD pulse lengths, but first data sampling is not
delayed. The second data sampling is correct.
Figure 27-3. Number of Standard Wait States is One
Note: 1. These numbers refer to the standard access cycles.
Standard Access Length with Two Wait States
EBI
5
1
(1)
2
(1)
3
(1)
MCKI
NWAIT
NCS
32-bit Access = Two 16-bit Accesses
Each Access Length = One Wait State + Assertion for One More Cycle
1
(1)
2
(1)
MCKI
NWAIT
NRD
2
(1)
First Data Sampling
(Erroneous)
1
(1)
2
(1)
2
(1)
Second Data
Sampling
(Correct)
EBI
5