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1745D–ATARM–04-Nov-05
AT91M55800A
• Internal peripherals in the four highest megabytes
In any of these address spaces, the ARM7TDMI operates in Little-Endian mode only.
7.6.1 Internal Memories
The AT91M55800A microcontroller integrates an 8-Kbyte SRAM bank. This memory bank is
mapped at address 0x0 (after the remap command), allowing ARM7TDMI exception vectors
between 0x0 and 0x20 to be modified by the software. The rest of the bank can be used for
stack allocation (to speed up context saving and restoring), or as data and program storage for
critical algorithms. All internal memory is 32 bits wide and single-clock cycle accessible. Byte
(8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed within one
cycle. Fetching Thumb or ARM instructions is supported and internal memory can store twice
as many Thumb instructions as ARM ones.
7.6.2 Boot Mode Select
The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI exe-
cutes the instruction stored at this address. This means that this address must be mapped in
nonvolatile memory after the reset.
The input level on the BMS pin during the last 10 clock cycles before the rising edge of the
NRST selects the type of boot memory (see Table 7-2).
The pin BMS is multiplexed with the I/O line PB18 that can be programmed after reset like any
standard PIO line.
7.6.3 Remap Command
The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt,
Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors
to be redefined dynamically by the software, the AT91M55800A microcontroller uses a remap
command that enables switching between the boot memory and the internal RAM bank
addresses. The remap command is accessible through the EBI User Interface, by writing one
in RCB of EBI_RCR (Remap Control Register). Performing a remap command is mandatory if
access to the other external devices (connected to chip selects 1 to 7) is required. The remap
operation can only be changed back by an internal reset or an NRST assertion.
7.6.4 Abort Control
The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI is
asserted when accessing an undefined address in the EBI address space.
No abort is generated when reading the internal memory or by accessing the internal peripher-
als, whether the address is defined or not.
Table 7-2. Boot Mode Select
BMS Boot Mode
1 External 8-bit memory on NCS0
0 External 16-bit memory on NCS0