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1745D–ATARM–04-Nov-05
AT91M55800A
27. Errata
The following known errata are applcable to:
• The following datasheets:
AT91M55800A Summary, 1745S
AT91M55800A, (This document)
AT91M55800A, Electrical Characteristics Rev.1727
• 176-lead LQFP and 176-ball BGA devices with the following markings:
27.1 ADC Characteristics and Behavior
The tracking time has a theoretical minimum duration. It equals one ADC Clock period and
is normally ensured by the ADC Controller.
It might randomly happen that this minimum duration cannot be guaranteed on the first
enabled channel. When this happens, the sampling and hold process is too short and the
conversion result is wrong.
Problem Fix/Work Around
To use only one channel, the user has to enable two channels and then must use the sec-
ond channel only.
In the event that all of the ADC channels need to be used, only three channels will be
available.
A software workaround allows all the channels to be used. It consists of performing several
conversions and averaging the samples on the first enabled channel. This method does
not support fast conversion. However, signals from temperature sensors, which are slow
signals, can be handled by averaging a number of samples.
27.2 Warning: Additional NWAIT Constraints
When the NWAIT signal is asserted during an external memory access, the following EBI
behavior is correct:
– NWAIT is asserted before the first rising edge of the master clock and respects the
NWAIT to MCKI rising setup timing as defined in the Electrical Characteristics
datasheet.
– NWAIT is sampled inactive and at least one standard wait state remains to be
executed, even if NWAIT does not meet the NWAIT to first MCKI rising setup
timing (i.e., NWAIT is asserted only on the second rising edge of MCKI).
In these cases, the access is delayed as required by NWAIT and the access operations are
correctly performed.
AT91M55800A-33AI
AT91M55800A-33AU
AT91M55800A-33CI
AT91M55800A-33CJ
Internal Product
Reference 56515B