Filter
Top Products
243
1745D–ATARM–04-Nov-05
AT91M55800A
If the first two conditions are not met during write accesses, the NWE signal is not affected by
the NWAIT assertion. The following example illustrates the number of standard wait states.
NWAIT is not asserted during the first cycle, but is asserted at the second and last cycle of the
standard access. The access is correctly delayed as the NCS line rises accordingly to the
NWAIT assertion. However, the NWE signal waveform is unchanged, and rises too early.
Figure 27-4. Description of the Number of Standard Wait States
27.3 Unpredictable Result in APMC State Machine on Switch from Oscillator to PLL
An automatic switch from the main oscillator output (CSS = 1) may cause an unpredictable
result in the APMC state machine. The automatic PLL to PLL transition is also effected by
this problem.
Problem Fix/Workaround
The user must either wait for the PLL lock flag to be set in the APMC status register or
switch to an intermediate 32 kHz oscillator output (CSS = 0).
27.4 Clock Switching with the Prescaler in the APMC is not Permitted
Switching from the selected clock (PRES = 0) to the selected clock divided by
4 (PRES = 2), 8 (PRES = 3) or 64 (PRES = 6) may lead to unpredictable results.
Problem Fix/Workaround
First, the user should switch to any other value (PRES = 1, 4 or 5) and wait for the actual
switch to perform (at least 64 cycles of the selected clock). Then, the user can write the
final prescaler value.
27.5 Initializing SPI in Master Mode May Cause a Mode Fault Detection
Problem Fix/Workaround
In order to prevent this error, the user must pull up the PA26/NPCS0/NSS pin to the V
DDIO
power supply.
Access Length = One Wait State + Assertion of the NWAIT for One More Cycle
EBI
5
MCKI
NWAIT
NWE
NCS
Erroneous NWE Rising