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1745D–ATARM–04-Nov-05
AT91M55800A
12.9.5 APMC Peripheral Clock Disable Register
Register Name: APMC_PCDR
Access Type: Write-only
Offset: 0x14
• Peripheral Clock Disable (per peripheral)
0 = No effect.
1 = Disables the peripheral clock.
12.9.6 APMC Peripheral Clock Status Register
Register Name: APMC_PCSR
Access Type: Read-only
Reset Value: 0x0
Offset: 0x18
• Peripheral Clock Status (per peripheral)
0 = The peripheral clock is disabled.
1 = The peripheral clock is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––
DAC1 DAC0 ADC1
15 14 13 12 11 10 9 8
ADC0 PIOB PIOA
–
TC5 TC4 TC3 TC2
76543210
TC1 TC0 SPI US2 US1 US0
––
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––
DAC1 DAC0 ADC1
15 14 13 12 11 10 9 8
ADC0 PIOB PIOA
–
TC5 TC4 TC3 TC2
76543210
TC1 TC0 SPI US2 US1 US0
––